Multi-image reticles

ABSTRACT

A reticle  100  includes two or more image patterns for different layers of an integrated circuit, each one in a separate image field  110 - 120 . These image layers are used in the production of the same integrated circuit. By placing multiple image layers on the same reticle, fewer reticles need to be produced and a prototype circuit can then be made more cheaply. Likewise the reduced set of reticles can be used where there is a limited run of circuits. If any or all reticle layers need to be replaced, then the replacement set is also cheaper.

FIELD OF THE INVENTION

The present invention relates to reticles and to the production ofreticles for use in lithography. In particular, it relates to suchreticles and the production of reticles that are useful in prototyping.

BACKGROUND

Lithography involves the making of a copy of a pattern in aphotosensitive photoresist coating on a substrate, usually asemiconductor substrate. Different areas of the coating are irradiatedaccording to the pattern in a reticle or mask. The irradiated areas arethen dissolved in a solvent during further processing; leaving only thenon irradiated areas of the coating behind. Integrated circuits arebuilt up by repeating this process a number of times using differentpatterns. A typical integrated circuit manufacturing process may involveup to thirty different patterns being added in this manner. Withincreasing complexity in circuits, this number is likely to increase.

A typical known reticle 10 is shown in FIG. 1. The reticle is a glassplate covered with a chrome layer 12. This chrome layer is removed incertain areas and during lithographic processing, light passes throughthese areas of the reticle. The pattern area 14 is in the middle of thereticle and includes an image pattern 16 (consisting of areas of removedand remaining chrome) to be copied into the photoresist coating on awafer. In this instance, the pattern 16 is repeated six times in atwo-by-three matrix. The size of reticle and pattern can vary andtherefore the number of repeating patterns will change accordingly.Usually one seeks to have the largest number of repeats of the patternpossible, to reduce the number of times a wafer has to be moved for onewafer to be irradiated over its entire surface.

The pattern area 14 includes a test frame 18 surrounding the repeatedpattern. This is made up of two horizontal scribelanes 20, one above andone below the pattern area and two vertical scribelanes 22, one on eachside of the pattern area 14. Each horizontal scribelane 20 consists ofvarious wafer making test structures: Critical Dimension (CD) andoverlay test structures (OCM boxes) with thickness test structuresstrung out between them. There are usually about thirty such structuresextending from one side of the pattern area 14 to the other. Thepatterns left by these test structures on a wafer are checked after thelayer has been processed to confirm that everything has been madecorrectly. If there are any problems with Critical Dimensions (CD) oralignment (Overlay), the wafers are reworked for that layer by removingthe resist and trying again. If the thickness structures are out ofspecification by being too thin, then extra film is deposited on thewafer to recover the situation. If the thickness structures are out ofspecification by being too thick, then the excess is polished or etchedoff. Each vertical scribelane 22 consists of electrical test areas.These are provided so that the electrical properties of the resultingetched layer can be tested. However, for these test areas the tests haveto wait until the end of the process, when the complete test structureshave been constructed down the sides of the completed integratedcircuits.

The chrome area around the test frame 18 extends a width of at least 3.5mm in the horizontal directions and 5 mm in the vertical direction,these minimum margins being known as the chrome border 24. The purposeof this is to make sure that unwanted light does not pass through thereticle through other gaps in the chrome to contaminate and ruin thewafer. Outside the chrome border 24, there is a bar code 26 to allow thereticle to be identified automatically and a written identifier 28 toallow easy human identification. Finally there are two positioningmarkers 30 to allow the reticle to be positioned accurately during use.In each case the bar code 26, identifier 28 and markers 30 are providedby chrome being removed.

Whilst a standard reticle as shown in FIG. 1 contains a single patternrepeated several times, for prototyping purposes it has also been knownto have two different image areas on a reticle, suitably separated, foruse in producing different circuits, possibly for different customers.Even within these image areas it is also known to have image fields fordifferent circuits, which are put down at the same time on the samewafer. These are known as Multi-Product Wafers (MPW).

U.S. Pat. No. 5,705,299, issued on 6 Jan. 1998, to Tew et al., describesa reticle with several different image areas on it. These image areasare all used to stitch a single layer pattern together, when the layerpattern is larger than the reticle field.

U.S. Pat. No. 6,368,754, issued on 9 Apr. 2002, to Imai, describes areticle with two different image areas on it. The two image areas areagain used on different areas of the same layer pattern.

FIG. 2 is a block diagram showing a typical flow relating to the designof a set of reticles. Firstly, a customer 40 determines that he requiresa particular circuit to be made in silicon. This circuit is designed ina design house 42 that is either internal or external to the customer40. The design of the circuit is then forwarded to a chip-finishingdepartment 44 as GDS design data. The GDS data contains details of everycomponent of the circuit, including the position co-ordinates for eachcomponent. In chip finishing 44, the reticles that are required for theproduction of each layer that makes up the circuit are designed.Typically there are between five to thirty of these. The informationdefining these reticles is passed as MEBES, reticle writing data, to amask shop 46 where the various Reticle designs are then etched intochrome on reticle glass. Finally, the reticles are used in a fabricationplant 48 to produce integrated circuits according to the design, onsemiconductor wafers.

Before an extended production run can be initiated, it is necessary totest integrated circuits that are produced. If there is a problem withthe circuit design, then usually one or more reticles will need to beredesigned and replaced. At the worst, the whole set of reticles willneed replacing. Typically, 50% of the prototyping runs of any set ofreticles fail in at least one respect. If this requires a completely newset of thirty of so reticles being produced, then this may typicallycost around US$350,000. It is therefore quite expensive to produce aninitial set of reticles and then to redesign and reproduce various ofthese, if not all of these, until a working design is achieved.

U.S. Pat. No. 4,758,863, issued on 19 Jul. 1988, to Nikkel, describesusing a reticle on which is a series of different mask patterns, all foruse in the same lithographic process. The different mask patterns arerotated relative to each other, at 180 degrees when there are just twodifferent patterns or at 90 degrees when there are four of them. Thereticle is rotated from one image pattern to the next, in layer orderuntil all have been used.

Japanese Patent Application Publication No. 02/2,556, published on 8Jan. 1990, in the name of Sharp Corporation describes a stepper reticlewith a number of different image patterns positioned sequentially sideby side. Individual patterns are exposed sequentially, while the otherpatterns are masked.

Japanese Patent Application Publication No. 04/404,453, published on 27Oct. 1992, in the name of Fujitsu Ltd describes a stepper reticle withfour different image patterns, two for each of two differentsemiconductor devices, positioned side by side. Individual patterns areexposed, while the other patterns are masked.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, there is provided areticle for use in the production of an integrated circuit. The reticlehas thereon different image patterns of different grades. The differentimage patterns are for creating patterns for different layers, duringthe production of the same integrated circuit.

According to a second aspect of the present invention, there is provideda reticle for use in the production of an integrated circuit, comprisinga plurality of different image patterns. The different image patternsare for creating patterns for different layers and are for use atdifferent times during the production of the same integrated circuit.The reticle lacks a second image pattern for use, between a first imagepattern which is on the reticle and a third image pattern which is onthe reticle, during the production of the same integrated circuit.

According to another aspect of the present invention, there is provideda reticle set for producing an integrated circuit, the set comprising aplurality of reticles, each as defined above.

According to again another aspect of the present invention, there isprovided a reticle set for use in producing an integrated circuit, theset comprising a plurality of reticles. Individual reticles of theplurality of reticles comprise a plurality of different image patternsthereon. The different image patterns of the plurality of reticles arefor creating patterns for different layers and are for use at differenttimes during the production of the same integrated circuit. Thedifferent image patterns of the plurality of reticles are for use in apredetermined order during the production of the integrated circuit. Inthe predetermined order a first image pattern which is on a first one ofthe plurality of reticles, is used before a second image pattern whichis on a second one of the plurality of reticles, which second pattern isused before a third image pattern which is on the first one of theplurality of reticles.

According to a further aspect of the present invention, there isprovided a method of producing a reticle for use in the production of anintegrated circuit using a plurality of different image patterns in apredetermined order. The method comprising scribing the reticle withdifferent image patterns of different grades. The different imagepatterns are for creating patterns for different layers during theproduction of the same integrated circuit.

According to again another aspect of the present invention, there isprovided a method of producing a reticle for use in the production of anintegrated circuit using a plurality of different image patterns in apredetermined order, the method comprising scribing the reticle with aplurality of different image patterns. The image patterns are scribedsuch that the different image patterns are for creating patterns fordifferent layers and are for use at different times during theproduction of the same integrated circuit. The image patterns arescribed such that the reticle lacks an image pattern for use, in thepredetermined order, between a first image pattern and a second imagepattern during the production of the same integrated circuit.

According to again another aspect of the present invention, there isprovided a method of producing a reticle set for use in producing anintegrated circuit, said set comprising a plurality of reticles. Themethod comprising scribing said plurality of reticles. Individualreticles of said plurality of reticles comprise a plurality of differentimage patterns thereon. The different image patterns of the plurality ofreticles are for creating patterns for different layers in creatingdifferent layers during the production of the same integrated circuit.At least one reticle comprises image patterns of different grades.

According to a further aspect of the present invention, there isprovided a method of producing a reticle set for use in producing anintegrated circuit, the set comprising a plurality of reticles, themethod comprising scribing the plurality of reticles. The image patternsare scribed such that individual reticles of the plurality of reticlescomprise a plurality of different image patterns thereon. The imagepatterns are scribed such that the different image patterns of theplurality of reticles are for creating patterns for different layers andare for use at different times during the production of the sameintegrated circuit. The image patterns are scribed such that thedifferent image patterns of the plurality of reticles are for use in apredetermined order during the production of the integrated circuit. Theimage patterns are scribed such that, in the predetermined order, afirst image pattern which is on a first one of the plurality ofreticles, is used before a second image pattern which is on a second oneof the plurality of reticles, which second pattern is used before athird image pattern which is on the first one of the plurality ofreticles.

According to yet a further aspect of the present invention, there isprovided a method for use in determining a reticle recipe, the recipebeing for use in producing a reticle set, where individual reticles ofsaid reticle set comprise a plurality of different image patternsthereon, the reticle set being for use in the production of anintegrated circuit using a plurality of different image patterns. Themethod comprises deciding which image patterns are to be included on asame reticle of the reticle set. When making this decision imagepatterns of different grades are permitted to be included on a samereticle.

According to another aspect of the present invention, there is provideda method for use in determining a reticle recipe, the recipe being foruse in producing a reticle set, where individual reticles of saidreticle set comprise a plurality of different image patterns thereon,the reticle set being for use in the production of an integrated circuitusing a plurality of different image patterns in a predetermined order.The method comprises: deciding which image patterns are to be includedon a same reticle of the reticle set. When making this decision firstand third image patterns are permitted to be placed on a same reticlewhilst a second image pattern which, within said predetermined order isbetween the first and third image patterns, is not to be placed on saidsame reticle.

According to yet another aspect of the present invention, there isprovided a method for use in determining a reticle recipe, the recipebeing for use in producing a reticle set, where individual reticles ofthe reticle set comprise a plurality of different image patternsthereon, the reticle set being for use in the production of anintegrated circuit using a plurality of different image patterns in apredetermined order. The method comprises deciding which image patternsare to be put on a same reticle of the reticle set, whilst notpermitting line and space image layer patterns to be on a same reticleof the reticle set as contact image layer patterns.

According to yet another aspect of the present invention, there isprovided software operable according to either of the above two methodsfor use in determining a reticle recipe. The software may, for instance,be stored on a suitable medium, such as a CD-ROM or floppy disc ordownloaded via the Internet.

According to a further aspect of the present invention, there isprovided a method of making an integrated circuit using a plurality ofreticles, wherein individual reticles of the plurality of reticlescomprise a plurality of different image patterns thereon. The methodcomprises imaging a first layer pattern of an integrated circuit on anarea of a substrate, after imaging the first layer pattern, imaging asecond layer pattern of the integrated circuit on the area of thesubstrate and after imaging the second layer pattern, imaging a thirdlayer pattern of the integrated circuit on the area of the substrate.Imaging the first layer pattern uses a first image pattern which is on afirst one of the plurality of reticles. Imaging the second layer patternuses a second image pattern which is on a second one of the plurality ofreticles. Imaging the third layer pattern uses a third image patternwhich is on the first one of the plurality of reticles.

According to another further aspect of the present invention, there isprovided a reticle for use in the production of an integrated circuit,having at least first and second different image patterns thereon, foruse in creating patterns for different layers and at different timesduring the production of the same integrated circuit.

According to an even further aspect of the present invention, there isprovided a method of producing a production integrated circuit. Thiscomprises: providing an integrated circuit using a plurality of reticlesor a reticle set of one of or produced using one of the above aspects,as a prototype integrated circuit, making a further set of reticles,based on the reticles used to produce the prototype integrated circuit;and using the further set of reticles to produce the productionintegrated circuit, each reticle of the further set of reticles beingused only once in producing the production integrated circuit.

Further aspects of the invention include a reticle produced using amethod of one or more of the above-mentioned aspects, a reticle setproduced using a method of one or more of the above-mentioned aspectsand an integrated circuit produced using a method of one or more of theabove-mentioned aspects.

Thus a reticle of at least one aspect of the invention includes two ormore image patterns for different layers of an integrated circuit, eachone usually in a separate image field. These image patterns are used inthe production of the same integrated circuit. The image patterns areused in a predetermined order. Between at least two of the imagepatterns on the reticle, an image pattern on a different reticle isused, within that predetermined order. By placing multiple imagepatterns on the same reticle, fewer reticles need to be produced and aprototype circuit can then be made more cheaply. Likewise the reducedset of reticles can be used where there is a limited run of circuits. Ifany or all reticle layers need to be replaced, then the replacement setis also cheaper.

DESCRIPTION OF THE DRAWINGS

The present invention is further described by way of non-limitativeexample with reference to the accompanying drawings, in which:

FIG. 1 shows a typical known reticle;

FIG. 2 is a block diagram representing the flow of orders and data inreticle design;

FIG. 3 shows a reticle according to an embodiment of the presentinvention;

FIG. 4 is an enlarged view of an area A within FIG. 3;

FIG. 5 is an enlarged view of a first area within FIG. 4; and

FIG. 6 is an enlarged view of a second area within FIG. 4.

DETAILED DESCRIPTION

FIG. 3 shows a reticle according to an embodiment of the presentinvention. It shares many of the features of the prior art shown in FIG.1 but differs significantly in that the six patterns shown are alldifferent, being used for different layers of the same circuit.

In FIG. 3, the reticle 100 is a glass plate covered with a chrome layer102. A bar code 104 allows automatic identification, whilst a writtenidentifier 106 allows human identification. Positioning markers 108allow the reticle to be positioned accurately during use.

There are six distinct image fields 110-120 each containing a differentimage pattern for a different layer and thereby for use at differenttimes. In this instance, image field 110 contains line layer 1 pattern,image field 112 contains line layer 2 pattern, image field 114 containsline layer 4 pattern, image field 116 contains line layer 3 pattern,image field 118 contains line layer 5 pattern and image field 120contains line layer 7 pattern (Reticle 1 of Table 1—see later). Betweeneach image field, there is sufficient space for the chrome borderrequirements. In this embodiment the image fields are orientated in thesame direction, although in other embodiments they may be rotatedrelative to each other if desired.

Area A, encompassing image field 120, is shown in more detail in FIG. 4.The general structure of the contents of each image field is the same,although the specific details of each image pattern and test frame willdiffer.

FIG. 4 shows area A of FIG. 3 in greater detail. Image field 120 is madeup of a lithographic pattern 130 with a test frame of two horizontalscribelanes 132 a, 132 b and two vertical scribelanes 134 a, 134 b(although in this embodiment the right-hand vertical scribelane 134 b isempty). Thus relevant test structures for each pattern surround eachpattern individually, rather then a single set of test structuressurrounding all six patterns, as in FIG. 1.

FIG. 5 schematically shows the lower horizontal scribelane 132 b ingreater detail. Both horizontal scribelanes 132 a, 132 b contain thesame number of test structures as in the prior art. However, rather thenbeing strung out horizontally, the structures in the present inventionmay be bricked out, extending across the surface of the reticle in thevertical direction. Thus, whereas the overlay and critical dimensionstructures in the prior art have the thickness boxes strung out betweenthem horizontally, in this instance, the overlay and critical dimensionstructures (OCM boxes) 142 a, 142 b lie above the thickness structure144 in the vertical direction across the surface of the reticle. Thereare two sets of overlay and critical dimension structures 142 a, 142 b,extending horizontally above the thickness structure across the reticle,which are separated slightly from each other in the horizontaldirection. The overlay and critical dimension structures 142 a, 142 band thickness structure 144 extend in two single rows, although, ifnecessary, there can be more than one row of each in a singlescribelane.

The scribelane of FIG. 5 is the lower horizontal scribelane 132 b. Theupper one 132 a is a mirror image of the lower one, reflected across ahorizontal axis. Thus in the upper scribelane 132 a, the two overlay andcritical dimension structures are below the thickness structure. The twothickness structures, of the upper and lower horizontal scribelanesbetween them make up a single row of test structures when put down ontoa wafer.

Typically, a horizontal scribelane has a minimum length of 16 mm and adepth of 100 μm (microns). In the presence instance, the scribelane is 6mm long, with the thickness of 200 μm (microns). Because the verticaldepth is relatively small, it does not matter if the test structures arestacked in several layers across the surface. The length of thethickness box structure is 5.5 mm and combined length of the two OCMstructures on a single line of the scribelane is 5 mm, so there isalmost complete overlap. However, the OCM boxes 142 a, 142 b arepositioned as near to the image field corners as possible, therebyoverhanging the ends of the thickness box structure 144. Thus the gapbetween the two OCM boxes 142 a, 142 b is more than 0.5 mm. Around 5 or6 mm is the normal minimum length of horizontal scribelane, since thatis the minimum length of a typical thickness box. However, it can beshorter, if the constituent boxes of the test structure allow this. Ifthe image pattern 130 itself is not as wide as the minimum width of thehorizontal scribelane, then the pattern can be repeated within the sameimage field 120, as can the image patterns in the same various otherimage fields, as in the prior art, with a single test frame surroundingeach set of repeated patterns.

FIG. 6 shows a schematic block diagram for the left-hand verticalscribelane 134 a. As with the prior art, this consists of a number ofelectrical test areas. Again, because the length of the scribelaneavailable to the test structures is shorter then in the prior art, theelectrical test structures 150 are stacked outwards, this time in thehorizontal direction of the reticle. Although in this embodiment all theelectrical test areas are in this left-hand vertical scribelane 134 a,these structures could be shared with or wholly within the right-handvertical scribelane 134 b.

The scribelanes in the present invention are organised differently andpositioned differently from in the prior art. However, differentpositioning and differing lengths of scribelane already exist in theprior art and thus the scribelanes of the present invention can easilybe tested without needing to adjust any machines except for theprogramming of the specific test. Scribelanes of the present inventionare not limited to the vertical and horizontal scribelanes as shown. Forinstance, they can swap positions or be in different formats.

The number of image fields possible on one reticle is determined bycalculating the size of each image field by adding the size of theengineering test structures to that of the chip (and scalingaccordingly, where there is a size reduction during exposure) andcomparing this with the maximum available reticle area, based on theexposure tool and the necessary borders around each field to preventnuisance patterns.

The reticle of FIG. 3 contains patterns for six different layers, all tobe used on the same circuit. Ideally all the patterns on a singlereticle would be used consecutively, so that for a thirty layersprocess, there would be just five reticles with the first six processeson reticle 1, the second six on reticle 2 etc. Unfortunately, this isnot always possible for various reasons, in which case it becomesnecessary to group layers into reticle recipes, according to thosepatterns that can be placed on the same reticle. TABLE 1 Table 1 is atable showing the recipes for a set of six reticles, having twenty-ninedifferent image patterns between them (image 1 on reticle 2 is usedtwice). Prev Proposed Reticle Reticle CD Order Image Layer Grade GradeType Material Target (4×) of use Reticle Barcode: 1 0041M11A 1 LineLayer 2 E G Line/Space Binary 1.728 2 2 Line Layer 4 E G Line/SpaceBinary 3.600 4 3 Line Layer 1 F G Line/Space Binary 1.008 1 4 Line Layer7 G G Line/Space Binary 0.720 7 5 Line Layer 3 E G Line/Space Binary3.600 3 6 Line Layer 5 D G Line/Space Binary 1.728 5 Reticle Barcode: 20041M12A 1 Line Layer 6 E E Line/Space Binary 1.728 6 & 14 2 Line Layer10 E E Line/Space Binary 1.728 10 3 Line Layer 11 E E Line/Space Binary1.728 11 4 Line Layer 13 E E Line/Space Binary 1.728 13 5 Line Layer 12E E Line/Space Binary 1.728 12 6 Line Layer 14 D E Line/Space Binary1.728 15 Reticle Barcode: 3 0041M13A 1 Line Layer 28 B D Line/SpaceBinary NA 29 2 Line Layer 8 D D Line/Space Binary 1.728 8 3 Line Layer 9D D Line/Space Binary 1.728 9 4 Line Layer 29 B D Line/Space Binary3.600 30 Reticle Barcode: 4 0041M14A 1 PSM Layer 1 G G Contact PhaseShift 1.044 16 (PSM) 2 PSM Layer 2 G G Contact Phase Shift 1.044 17(PSM) Reticle Barcode: 5 0041M15A 1 Line Layer 17 F F Line/Space Binary1.152 18 2 Line Layer 19 F F Line/Space Binary 1.152 20 3 Line Layer 21F F Line/Space Binary 1.152 22 4 Line Layer 23 F F Line/Space Binary1.152 24 5 Line Layer 25 F F Line/Space Binary 2.304 26 6 Line Layer 27F F Line/Space Binary 2.304 28 Reticle Barcode: 6 0041M16A 1 ContactLayer 1 F F Contact Binary 1.080 19 2 Contact layer 2 F F Contact Binary1.080 21 3 Contact Layer 3 F F Contact Binary 1.080 23 4 Contact Layer 4F F Contact Binary 1.080 25 5 Contact Layer 5 F F Contact Binary 2.16027

Table 1 includes various components:

-   -   “Bar code” indicates the identifier for the reticle. Reticle        naming is configured to fit within fabrication tool protocols to        allow transparent wafer processing    -   “Image” indicates the positioning of the relevant image field on        the reticle. In this embodiment, image 1 is top right, image 2        is top left, image 3 is middle right, image 4 is middle left,        image 5 is bottom right and image 6 is bottom left. The ordered        sequence of positions is thus between consecutive images and        rows.    -   “Layer” identifies the type of layer that is to be formed.    -   “Prev grade” indicates the grade of reticle normally used for an        individual layer. Reticles can generally be graded from grade A        (lowest grade) to grade G (highest grade). “Prev grade” in        effect indicates the grade of the layer.    -   “New grade” indicates the grade of reticle that is to be used        for that layer, the same grade to be used for the whole of any        one reticle and the grade having to be suitable for all the        image layers present on that reticle.    -   “CD Target (4×)” indicates the critical dimensions of the        features on the reticle, which in this example are 4× the target        critical dimensions to be achieved in the resist during        lithography.    -   “Order of use” indicates the order of use of the different image        layers within the whole process of using the reticle set to make        an integrated circuit. Thus, for example, Reticle 2 is used for        the sixth process, before Reticle 1 is finished with. Further,        even within a reticle, the image layers do not necessarily        appear in the order in which they are to be used (see Reticles 1        and 2). A program deciding where to place the image layers may        decide otherwise.

These reticles of Table 1 are for use with 180 nm technology. They wereformulated based on the rules and preferences below. The compatibilityof the layers that are put on one reticle is checked to allowtransparent manufacturing of the reticles by the mask shop.

Rule 1—Line and spaces cannot be mixed with contact layers.

-   -   Every pattern can be generally categorised into either providing        lines and spaces or providing contacts. These cannot be mixed on        the same reticle because the reticle manufacturing process is        different for the different types of process. Thus in Table 1,        all the image layers of reticles 1, 2, 3 and 5 are defined as        line and space layers, whilst all those in reticles 4 and 6 are        defined as contact layers.

Rule 2—Do not downgrade a layer, always put it on the same or a bettergrade of reticle.

-   -   Different layers require different grades of reticle, in terms        of mean to target (how close to the designed size the actual        size on the reticle is), uniformity (what the CD variation is        across the plate, typically sampled at >20 sites), registration        (how well centred the pattern is, with respect to the alignment        marks on the reticle) and defects (how many defects there are on        the reticle, and what the sizes of these defects are). Whilst an        image layer pattern can still work when put on a better grade of        reticle, it cannot work, or not as well if on a lesser grade of        reticle than is normally required. Individual reticles        themselves are generally only of one grade.

Rule 3—Reticle types cannot be mixed. It is not possible to mix phaseshift modulation (PSM) reticles with binary reticles.

-   -   Thus Reticle 4 in Table 1 only contains two image layers,        because they alone in example, as it only has two image fields        on it, it is classified as a small field size reticle.

Rule 7 Try, where possible to put most critical (higher grade) layerstowards the centre of a reticle.

-   -   If a reticle contains layers of different grades, less critical,        lower grade layers being present with more critical higher grade        layers, to reduce the number of reticles used, the higher grade        layers are better off nearer the centre of the reticle. This is        because mask writing tools tend to write more accurately near        the centre of a reticle. If all the layers are of the same        grade, then usually some will have to be further from the centre        than others.

Thus the example reticle set of Table 1 has six reticles, of which threehave six layers, one has five layers, one has four layers and one hastwo layers. Use of the present invention, may quite often lead toreticle sets with at least three reticles having different numbers ofimage layers or patterns thereon.

Reticle recipes can be determined according to the invention usingsoftware running on a standard desktop computer. The software is writtento incorporate the above rules, with the preference rules absent,present and individually optional or present and obligatory.

Whilst the rules in the cases above are particularly relevant to 180 nmtechnology, they are not limited thereto. Many of the rules still applyto smaller and larger technologies, although for larger technologies,such as 2 μm (micron) technologies, PSM is not used and therefore Rule 3becomes redundant. Others of the rules might also become redundant inparticular situations and likewise new rules may be added also. Thepresent invention is useful for almost all sizes of technology, whether2 μm (micron) or 180 nm or even smaller technologies. Likewise, it canbe used with electromagnetic radiation lithography of variouswavelengths.

Multi-layer reticles of the present invention can be designed, producedand used using existing systems. In terms of what is required of thecircuit by the customer, that is not changed at all, nor does thecircuit design. The only extra steps occur in chip finishing, because itis now necessary to determine reticle recipes for distributing the imagelayers and manipulate incoming GDS data. All the engineering structuresthat are needed for wafer manufacturing have to be Included in everyimage field in each reticle. The mask shop works in the same way, inthat it produces the mask according to the in put data, although themask contains six different patterns, as opposed to one pattern repeatedsix times. Finally, the fabrication plant behaves in the same way,except that the exposure tool has to be able to select different ones ofthe image areas at different stages of the process. Further, a smallerarea on any wafer is exposed in any one step, so that it takes roughlyfour times as long to produce a completed wafer of integrated circuits.This is because the number of circuits per area of wafer tends to besmaller (due to the additional spacing between each one). However, theactual processing time for creating a prototyping wafer or a limited runof integrated circuits is generally not critical.

In this manner, a complete set of reticles for a process can be builtfor much less than it previously cost, even allowing for the additionalwork in deciding on the reticle recipes. For example, the cost may beone quarter or less of the cost of a full set of prior art reticles.

The present invention is ideally suited for prototyping, whereby oncethe reticle set has been tested and approved, a normal full set ofthirty reticles or so may then be produced to the same design (but withone repeating pattern per reticle). This is necessary because for largeproduction runs, the multi-layer reticles would be too slow. However,the multi-layer reticles can be used for limited production runs quitereadily. The product is not in any way inferior to that produced by arepeated pattern reticle set, and can be tested just as completely andreadily.

As well as the multi-layer reticle sets themselves being an improvement,they also give rise to an improved business approach. Parties wishing tohave reticle sets made up for them can have the option of a normal fullreticle set or a multi-layer reticle sets according to their ownsituation and whether the design has already been proven. The decisioncould even be just a tick box option on an order form.

Whilst the invention has been embodied with reticles having two, fourand six image patterns, the present invention will also work with othernumbers, for instance, three or five patterns or even more than six.

In this description, the terms horizontal and vertical and upper andlower, etc appear. This is for ease of understanding, based on theorientation of the figures and is not intended to be limiting unlessthat would be understood from the context. Thus other embodiments of theinvention could readily have the different features rotated 90 degreesrelative to what is shown (or other angular amounts if appropriate). Theorientation is generally not important.

It would be quite clear to the person skilled in the art that variousmodifications can be made to the present invention without departingfrom the scope of the invention as described and claimed.

1. A reticle for use in the production of an integrated circuit, havingthereon different image patterns of different grades, for creatingpatterns for different layers during the production of the sameintegrated circuit.
 2. A reticle for use in the production of anintegrated circuit, comprising a plurality of different image patterns,wherein the different image patterns are for creating patterns fordifferent layers and are for use at different times during theproduction of the same integrated circuit; and said reticle lacks asecond image pattern for use, between a first image pattern which is onthe reticle and a third image pattern which is on the reticle, duringthe production of the same integrated circuit.
 3. A reticle according toclaim 2, wherein the plurality of different image patterns compriseimage patterns of different grades.
 4. A reticle according to claim 1,wherein the higher grade image patterns are at least as near to thecentre of the reticle as are the lower grade image patterns.
 5. Areticle according to claim 4, wherein the higher grade image patternsare nearer to the centre of the reticle than are the lower grade imagepatterns.
 6. A reticle according to claim 1, wherein the reticlecomprises a plurality of each of said different image patterns.
 7. Areticle according to claim 1, further comprising at least one scribelanefor each different image pattern, the scribelanes including a thicknessbox structure in the length wise direction of the scribelane.
 8. Areticle according to claim 7, wherein at least one critical dimensionstructure overlaps the thickness box structure in the length wisedirections of the scribelanes.
 9. A reticle according to claim 7,wherein at least one overlay structure overlaps the thickness boxstructure in the length wise directions of the scribelanes.
 10. Areticle according to claim 1, wherein: the different image patterns havean order of use in producing a circuit; the reticle includes an orderedsequence of image areas between consecutive image areas and rows; andthe order of the different image patterns within the sequence of imageareas is different from the order of use of the image patterns relativeto each other.
 11. A reticle according to claim 1, wherein the reticleis of a single grade.
 12. A reticle for use in the production of anintegrated circuit, having at least first and second different imagepatterns thereon, for use in creating patterns for different layers andat different times during the production of the same integrated circuit.13. A reticle set for use in producing an integrated circuit, said setcomprising a plurality of reticles, wherein individual reticles of saidplurality of reticles comprise a plurality of different image patterns;the different image patterns of individual reticles of said plurality ofreticles are for creating patterns for different layers and are for useat different times during the production of the same integrated circuit;and a first reticle of said plurality of reticles comprises a firstimage pattern and a third image pattern and lacks a second image patternfor use between said first and second image patterns during theproduction of the same integrated circuit.
 14. A reticle set accordingto claim 13, wherein the different image patterns of the plurality ofreticles are for use in a predetermined order during the production ofsaid integrated circuit; and in said predetermined order, a first imagepattern which is on a first one of said plurality of reticles, is usedbefore a second image pattern which is on a second one of said pluralityof reticles, which second pattern is used before a third image patternwhich is on said first one of said plurality of reticles.
 15. A reticleset for use in producing an integrated circuit, said set comprising aplurality of reticles; wherein individual reticles of said plurality ofreticles comprise a plurality of different image patterns thereon; thedifferent image patterns of the plurality of reticles are for creatingpatterns for different layers and are for use at different times duringthe production of the same integrated circuit; the different imagepatterns of the plurality of reticles are for use in a predeterminedorder during the production of said integrated circuit; and in saidpredetermined order, a first image pattern which is on a first one ofsaid plurality of reticles is used before a second image pattern whichis on a second one of said plurality of reticles, which second patternis used before a third image pattern which is on said first one of saidplurality of reticles.
 16. A reticle set according to claim 13, whereindifferent reticles of said set have different numbers of image patternsthereon.
 17. A reticle set according to claim 16, comprising at leastthree reticles with different numbers of image patterns thereon.
 18. Amethod of producing a reticle for use in the production of an integratedcircuit using a plurality of different image patterns in a predeterminedorder, the method comprising scribing said reticle with different imagepatterns of different grades, such that the different image are forcreating patterns for different layers during the production of the sameintegrated circuit.
 19. A method of producing a reticle for use in theproduction of an integrated circuit using a plurality of different imagepatterns in a predetermined order, the method comprising scribing saidreticle with a plurality of different image patterns such that: thedifferent image patterns are for creating patterns for different layersand are for use at different times during the production of the sameintegrated circuit; and said reticle lacks an image pattern for use, insaid predetermined order, between a first image pattern and a secondimage pattern during the production of the same integrated circuit. 20.A method of producing a reticle set for use in producing an integratedcircuit, said set comprising a plurality of reticles, the methodcomprising scribing said plurality of reticles such that: individualreticles of said plurality of reticles comprise a plurality of differentimage patterns thereon; the different image patterns of the plurality ofreticles are for creating patterns for different layers during theproduction of the same integrated circuit; and at least one reticlecomprises image patterns of different grades.
 21. A method of producinga reticle set for use in producing an integrated circuit, said setcomprising a plurality of reticles, the method comprising scribing saidplurality of reticles such that: individual reticles of said pluralityof reticles comprise a plurality of different image patterns thereon;the different image patterns of the plurality of reticles are forcreating patterns for different layers and are for use at differenttimes during the production of the same integrated circuit; thedifferent image patterns of the plurality of reticles are for use in apredetermined order during the production of said integrated circuit;and in said predetermined order, a first image pattern which is on afirst one of said plurality of reticles is used before a second imagepattern which is on a second one of said plurality of reticles, whichsecond pattern is used before a third image pattern which is on saidfirst one of said plurality of reticles.
 22. A method for use indetermining a reticle recipe, the recipe being for use in producing areticle set, where individual reticles of said reticle set comprise aplurality of different image patterns thereon, the reticle set being foruse in the production of an integrated circuit using a plurality ofdifferent image patterns, the method comprising: deciding which imagepatterns are to be included on a same reticle of the reticle set and, indoing so, permitting image patterns of different grades to be includedon a same reticle.
 23. A method for use in determining a reticle recipe,the recipe being for use in producing a reticle set, where individualreticles of said reticle set comprise a plurality of different imagepatterns thereon, the reticle set being for use in the production of anintegrated circuit using a plurality of different image pattern layersin a predetermined order, the method comprising: deciding which imagepatterns are to be included on a same reticle of the reticle set and, indoing so, permitting first and third image patterns to be placed on asame reticle whilst a second image pattern which, within saidpredetermined order is between the first and third image patterns, isnot to be placed on said same reticle.
 24. A method according to claim23, further comprising, in deciding which image patterns are to beincluded on a same reticle of the reticle set, permitting image patternsof different grades to be included on a same reticle.
 25. A methodaccording to claim 22, further comprising determining the orders of theimage patterns on the reticles, such that, on a reticle that is toinclude image patterns of different grades, the higher grade imagepatterns are determined to be at least as near to the centre of thereticle as are the lower grade image patterns.
 26. A method according toclaim 25, wherein the higher grade image patterns are determined to benearer to the centre of the reticle than are the lower grade imagepatterns.
 27. A method according to claim 23, further comprising notallowing line and space image layer patterns to be on a same reticle ofthe reticle set as contact image layer patterns.
 28. A method accordingto claim 23, further comprising not allowing phase shift modulationlayer patterns on a same reticle of the reticle set as binary layerpatterns.
 29. A method according to claim 23, further comprisingchoosing the grade of a reticle of the reticle set to be the minimumgrade necessary or preferred according to the image patterns to beplaced thereon.
 30. Computer software for determining a reticle recipefor use in producing a reticle set, where individual reticles of saidreticle set comprise a plurality of different image patterns thereon,the reticle set being for use in the production of an integrated circuitusing a plurality of different image patterns, the software beingoperable in accordance with a method comprising: deciding which imagepatterns are to be included on a same reticle of the reticle set and, indoing so, permitting image patterns of different grades to be includedon a same reticle.
 31. A method of producing an integrated circuit usinga plurality of reticles, wherein individual reticles of said pluralityof reticles comprise a plurality of different image patterns thereon,the method comprising: imaging a first layer pattern of an integratedcircuit on an area of a substrate using a first image pattern which ison a first one of said plurality of reticles; after imaging the firstpattern, imaging a second layer pattern of the integrated circuit on thearea of the substrate using a second image pattern which is on a secondone of said plurality of reticles; and after imaging the second layerpattern, imaging a third layer pattern of the integrated circuit on thearea of the substrate using a third image pattern which is on said firstone of said plurality of reticles.
 32. A method of producing aproduction integrated circuit comprising the steps of: producing aprototype integrated circuit using a first reticle set; making a furtherset of reticles, based on the first reticle; and using said further setof reticles to produce said production integrated circuit, individualreticles of the further set of reticles being used only once inproducing said production integrated circuit; wherein the first reticleset comprises a plurality of prototype reticles, with individualreticles of said plurality of reticles comprising a plurality ofdifferent image patterns thereon; and producing the prototype integratedcircuit comprises: imaging a first layer pattern of an integratedcircuit on an area of a substrate using a first image pattern which ison a first one of said plurality of prototype reticles; after imagingthe first layer pattern, imaging a second layer pattern of theintegrated circuit on the area of the substrate using a second imagepattern which is on a second one of said plurality of prototypereticles; and after imaging the second layer pattern, imaging a thirdlayer pattern of the integrated circuit on the area of the substrateusing a third image pattern which is on said first one of said pluralityof prototype reticles.